Data processing apparatus for transmitting/receiving compressed pixel data groups of picture over display interface and related data processing method

ABSTRACT

A data processing apparatus has a mapper, a plurality of compressors, and an output interface. The mapper receives pixel data of a plurality of pixels of a picture, and splits the pixel data of the pixels of the picture into a plurality of pixel data groups. The compressors compress the pixel data groups and generate a plurality of compressed pixel data groups, respectively. The output interface packs the compressed pixel data groups into at least one output bitstream, and outputs the at least one output bitstream via a display interface.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. provisional application No.61/865,345, filed on Aug. 13, 2013 and incorporated herein by reference.

BACKGROUND

The disclosed embodiments of the present invention relate totransmitting and receiving data over a display interface, and moreparticularly, to a data processing apparatus for transmitting/receivingcompressed pixel data groups of a picture over a display interface and arelated data processing method.

A display interface is disposed between a first chip and a second chipto transmit display data from the first chip to the second chip forfurther processing. For example, the first chip may be a hostapplication processor, and the second chip may be a driver integratedcircuit (IC). The display data may be single view data fortwo-dimensional (2D) display or multiple view data for three-dimensional(3D) display. When a display panel supports a higher display resolution,2D/3D display with higher resolution can be realized. Hence, the displaydata transmitted over the display interface would have a larger datasize/data rate, which increases the power consumption of the displayinterface inevitably. If the host application processor and the driverIC are both located at a portable device (e.g., a smartphone) powered bya battery device, the battery life is shortened due to the increasedpower consumption of the display interface. Thus, there is a need for aninnovative design which can effectively reduce the power consumption ofthe display interface.

SUMMARY

In accordance with exemplary embodiments of the present invention, adata processing apparatus for transmitting/receiving compressed pixeldata groups of a picture over a display interface and a related dataprocessing method are proposed.

According to a first aspect of the present invention, an exemplary dataprocessing apparatus is disclosed. The exemplary data processingapparatus includes a mapper, a plurality of compressors, and an outputinterface. The mapper is configured to receive pixel data of a pluralityof pixels of a picture, and split the pixel data of the pixels of thepicture into a plurality of pixel data groups. The compressors areconfigured to compress the pixel data groups and generate a plurality ofcompressed pixel data groups, respectively. The output interface isconfigured to pack the compressed pixel data groups into at least oneoutput bitstream, and output the at least one output bitstream via adisplay interface.

According to a second aspect of the present invention, an exemplary dataprocessing apparatus is disclosed. The exemplary data processingapparatus includes an input interface, a plurality of de-compressors,and a de-mapper. The input interface is configured to receive at leastone input bitstream from a display interface, and un-pack the at leastone input bitstream into a plurality of compressed pixel data groups ofa picture. The de-compressors are configured to de-compress thecompressed pixel data groups and generate a plurality of de-compressedpixel data groups, respectively. The de-mapper is configured to mergethe de-compressed pixel data groups into pixel data of a plurality ofpixels of the picture.

According to a third aspect of the present invention, an exemplary dataprocessing method is disclosed. The exemplary data processing methodincludes: receiving pixel data of a plurality of pixels of a picture,and splitting the pixel data of the pixels of the picture into aplurality of pixel data groups; compressing the pixel data groups togenerate a plurality of compressed pixel data groups, respectively; andpacking the compressed pixel data groups into at least one outputbitstream, and outputting the at least one output bitstream via adisplay interface.

According to a fourth aspect of the present invention, an exemplary dataprocessing method is disclosed. The exemplary data processing methodincludes: receiving at least one input bitstream from a displayinterface, and un-packing the at least one input bitstream into aplurality of compressed pixel data groups of a picture; de-compressingthe compressed pixel data groups to generate a plurality ofde-compressed pixel data groups, respectively; and merging thede-compressed pixel data groups into pixel data of a plurality of pixelsof the picture.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a data processing systemaccording to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a pixel data splitting operationperformed by a mapper based on a first pixel data grouping design.

FIG. 3 is a diagram illustrating a pixel data merging operationperformed by a de-mapper based on the first pixel data grouping design.

FIG. 4 is a diagram illustrating a pixel data splitting operationperformed by a mapper based on a second pixel data grouping design.

FIG. 5 is a diagram illustrating a pixel data merging operationperformed by a de-mapper based on the second pixel data grouping design.

FIG. 6 is a diagram illustrating a first pixel section based pixel datagrouping design according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating a second pixel section based pixel datagrouping design according to an embodiment of the present invention.

FIG. 8 is a flowchart illustrating a control and data flow of the dataprocessing system shown in FIG. 1 according to an embodiment of thepresent invention.

FIG. 9 is a diagram illustrating a position-aware rate control mechanismaccording to an embodiment of the present invention.

FIG. 10 is a diagram illustrating an alternative design of step 806 inFIG. 8.

FIG. 11 is a diagram illustrating a modified compression mechanismaccording to an embodiment of the present invention.

FIG. 12 is a diagram illustrating an alternative design of step 808 inFIG. 8.

DETAILED DESCRIPTION

Certain terms are used throughout the description and following claimsto refer to particular components. As one skilled in the art willappreciate, manufacturers may refer to a component by different names.This document does not intend to distinguish between components thatdiffer in name but not function. In the following description and in theclaims, the terms “include” and “comprise” are used in an open-endedfashion, and thus should be interpreted to mean “include, but notlimited to . . . ”. Also, the term “couple” is intended to mean eitheran indirect or direct electrical connection. Accordingly, if one deviceis coupled to another device, that connection may be through a directelectrical connection, or through an indirect electrical connection viaother devices and connections.

The present invention proposes applying data compression to a displaydata and then transmitting a compressed display data over a displayinterface. As the data size/data rate of the compressed display data issmaller than that of the original un-compressed display data, the powerconsumption of the display interface is reduced correspondingly.However, there may be a throughput bottleneck for acompression/de-compression system due to long data dependency ofprevious compressed/reconstructed data. To minimize or eliminate thethroughput bottleneck of the compression/de-compression system, thepresent invention further proposes a data parallelism design. Forexample, the rate control intends to optimally sub-optimally adjust thebit rate of each compression unit so as to achieve the content-aware bitbudget allocation and therefore improve the visual quality. However, therate control generally suffers from the long data dependency. When theproposed data parallelism design is employed, there will be a compromisebetween the processing throughput and the rate control performance. Itshould be noted that the proposed data parallelism design is not limitedto enhancement of the rate control, any compression/de-compressionsystem using the proposed data parallelism design falls within the scopeof the present invention. Further details will be described as below.

FIG. 1 is a block diagram illustrating a data processing systemaccording to an embodiment of the present invention. The data processingsystem 100 includes a plurality of data processing apparatuses such asan application processor 102 and a driver integrated circuit (IC) 104.The application processor 102 and the driver IC 104 may be implementedin different chips, and the application processor 102 may communicatewith the driver IC 104 via a display interface 103. In this embodiment,the display interface 103 may be a display serial interface (DSI)standardized by a Mobile Industry Processor Interface (MIPI) or anembedded display port (eDP) standardized by a Video ElectronicsStandards Association (VESA).

The application processor 102 is coupled between a data source 105 andthe display interface 103, and supports compressed data transmission.The application processor 102 receives an input display data from theexternal data source 105, where the input display data may be image dataor video data that includes pixel data DI of a plurality of pixels of apicture to be processed. By way of example, but not limitation, the datasource 105 may be a camera sensor, a memory card or a wireless receiver.As shown in FIG. 1, the application processor 102 includes a displaycontroller 111, an output interface 112 and a processing circuit 113.The processing circuit 113 includes circuit elements required forprocessing the pixel data DI to generate a plurality of compressed pixeldata groups (e.g., two compressed pixel data groups DG₁′ and DG₂′ inthis embodiment). For example, the processing circuit 113 has a mapper114, a plurality of compressors (e.g., two compressors 115_1 and 115_2in this embodiment), a rate controller 116, and other circuitry 117,where the other circuitry 117 may have a display processor, additionalimage processing element(s), etc. The display processor may performimage processing operations, including scaling, rotating, etc. Forexample, the input display data provided by the data source 105 may bebypassed or processed by the additional image processing element(s)located before the display processor to generate a source display data,and then the display processor may process the source display data togenerate the pixel data DI to the mapper 114. In other words, the pixeldata DI to be processed by the mapper 114 may be directly provided fromthe data source 105 or indirectly obtained from the input display dataprovided by the data source 105. The present invention has no limitationon the source of the pixel data DI.

The mapper 114 acts as a splitter, and is configured to receive thepixel data DI of one picture and split the pixel data DI of one pictureinto a plurality of pixel data groups (e.g., two pixel data groups DG₁and DG₂ in this embodiment) according to a pixel data group settingDG_(SET). Further details of the mapper 114 will be described later.Since the pixel data DI is split into two pixel data groups DG₁ and DG₂,two compressors 115_1 and 115_2 are selected from multiple compressorsimplemented in the processing circuit 113, and enabled to compress thepixel data groups DG₁ and DG₂ to generate compressed pixel data groupsDG₁′ and DG₂′, respectively. In other words, the number of enabledcompressors depends on the number of pixel data groups.

Each of the compressors 115_1 and 115_2 may employ a losslesscompression algorithm or a lossy compression algorithm, depending uponthe actual design consideration. The rate controller 116 is configuredto apply bit rate control (i.e., bit budget allocation) to thecompressors 115_1 and 115_2, respectively. In this way, each of thecompressed pixel data groups DG₁′ and DG₂′ is generated at a desired bitrate. In this embodiment, compression operations performed by thecompressors 115_1 and 115_2 are independent of each other, thus enablingrate control with data parallelism. Since the long data dependency isalleviated, the rate control performance can be improved.

The output interface 112 is configured to pack/packetize the compressedpixel data groups DG₁′ and DG₂′ into at least one output bitstreamaccording to the transmission protocol of the display interface 103, andtransmit the at least one output bitstream to the driver IC 104 via thedisplay interface 103. By way of example, one bitstream BS may begenerated from the application processor 102 to the driver IC 104 viaone display port of the display interface 103.

Regarding the driver IC 104, it communicates with the applicationprocessor 102 via the display interface 103. In this embodiment, thedriver IC 104 is coupled between the display interface 103 and a displaypanel 106, and supports compressed data reception. By way of example,the display panel 106 may be implemented using any 2D/3D display device.When the application processor 102 transmits compressed display data(e.g., compressed pixel data groups DG₁′ and DG₂′ packed in thebitstream BS) to the driver IC 104, the driver IC 104 is configured toreceive the compressed display data from the display interface 103 anddrive the display panel 106 according to de-compressed display dataderived from de-compressing the compressed display data.

As shown in FIG. 1, the driver IC 104 includes a driver IC controller121, an input interface 122 and a processing circuit 123. The inputinterface 122 is configured to receive at least one input bitstream fromthe display interface 103 (e.g., the bitstream BS received by onedisplay port of the display interface 103), and un-pack/un-packetize theat least one input bitstream into a plurality of compressed pixel datagroups of a picture (e.g., two compressed pixel data groups DG₃′ andDG₄′ in this embodiment). It should be noted that, if there is no errorintroduced during the data transmission, the compressed pixel data groupDG₃′ generated from the input interface 122 should be identical to thecompressed pixel data group DG₁′ received by the output interface 112,and the compressed pixel data group DG₄′ generated from the inputinterface 122 should be identical to the compressed pixel data groupDG₂′ received by the output interface 112.

The processing circuit 123 may include circuit elements required fordriving the display panel 106. For example, the processing circuit 123has a de-mapper 124, a plurality of de-compressors (e.g., twode-compressors 125_1 and 125_2 in this embodiment), and other circuitry127, where the other circuitry 127 may have a display buffer, additionalimage processing element (s), etc. The de-compressor 125_1 is configuredto de-compress the compressed pixel data group DG₃′ to generate ade-compressed pixel data group DG₃, and the de-compressor 125_2 isconfigured to de-compress the compressed pixel data group DG₄′ togenerate a de-compressed pixel data group DG₄. In this embodiment, thede-compression operations performed by the de-compressors 125_1 and125_2 are independent of each other. In this way, the de-compressionthroughput is improved due to data parallelism.

The de-compression algorithm employed by each of the de-compressors125_1 and 125_2 should be properly configured to match the compressionalgorithm employed by each of the compressors 115_1 and 115_2. In otherwords, the de-compressors 125_1 and 125_2 are configured to performlossless de-compression when the compressors 115_1 and 115_2 areconfigured to perform lossless compression; and the de-compressors 125_1and 125_2 are configured to perform lossy de-compression when thecompressors 115_1 and 115_2 are configured to perform lossy compression.If there is no error introduced during the data transmission and alossless compression algorithm is employed by the compressors 115_1 and115_2, the de-compressed pixel data group DG₃ fed into the de-mapper 124should be identical to the pixel data group DG₁ generated from themapper 114, and the de-compressed pixel data group Da₄ fed into thede-mapper 124 should be identical to the pixel data group DG₂ generatedfrom the mapper 114.

The de-mapper 124 acts as a combiner, and is configured to merge thede-compressed pixel data groups into pixel data DO of a plurality ofpixels of a reconstructed picture based on the pixel data groupingsetting DG_(SET) that is employed by the mapper 114. The pixel datagrouping setting DG_(SET) employed by the mapper 114 may be transmittedfrom the application processor 102 to the driver IC 104 via an in-bandchannel (i.e., display interface 103) or an out-of-band channel 107(e.g., an I²C (Inter-Integrated Circuit) bus). Specifically, the displaycontroller 111 controls the operation of the application processor 102,and the driver IC controller 121 controls the operation of the driver IC104. Hence, the display controller 111 may first check a de-compressioncapability and requirement of the driver IC 104, and then determine thenumber of pixel data groups in response to a checking result. Inaddition, the display controller 111 may further determine the pixeldata grouping setting DG_(SET) employed by the mapper 114 to generatethe pixel data groups that satisfy the de-compression capability andrequirement of the driver IC 104, and transmit the pixel data groupingsetting DG_(SET) over display interface 103 or out-of-band channel 107.When receiving a query issued from the display controller 111, thedriver IC controller 121 may inform the display controller 111 of thede-compression capability and requirement of the driver IC 104. Inaddition, when receiving the pixel data grouping setting DG_(SET) fromdisplay interface 103 or out-of-band channel 107, the driver ICcontroller 121 may control the de-mapper 124 to perform the pixel datamerging operation based on the received pixel data grouping settingDG_(SET).

The present invention proposes several pixel data grouping designs thatcan be used to split pixel data of a plurality of pixels of one pictureinto multiple pixel data groups. Examples of the proposed pixel datagrouping designs are detailed as below.

In a first pixel data grouping design, the mapper 114 splits the pixeldata DI of pixels of one picture by dividing bit depths/bit planes intodifferent groups. FIG. 2 is a diagram illustrating a pixel datasplitting operation performed by the mapper 114 based on the first pixeldata grouping design. As shown in FIG. 2, the width of a picture 200 isW, and the height of the picture 200 is H. Thus, the picture 200 has W×Hpixels 201. In this embodiment, pixel data of each pixel 201 has aplurality of bits corresponding to different bit planes. For example,each pixel 201 has 12 bits B₀-B₁₁ for each color channel R/G/B. The bitsB₀-B₁₁ correspond to different bit planes Bit-plane[0]-Bit-plane[11].Specifically, the least significant bit (LSB) B₀ corresponds to the bitplane Bit-plane[0], and the most significant bit (MSB) B₁₁ correspondsto the bit plane Bit-plane[11]. When the first pixel data groupingdesign is employed, the display controller 111 controls the pixel datagrouping setting DG_(SET) to instruct the mapper 114 to split bits ofthe pixel data of each pixel into a plurality of bit groups (e.g., twobit groups BG₁ and BG₂ in this embodiment), and distribute the bitgroups to the pixel data groups (e.g., pixel data groups DG₁ and DG₂ inthis embodiment), respectively. Concerning bits B₀-B₁₁ of color channelsR, G, B of each pixel 201, the mapper 114 may categorize even bits B₀,B₂, B₄, B₆, B₈, B₁₀ as one bit group BG₁, and categorize odd bits B₁,B₃, B₅, B₇, B₉, B₁₁ as another bit group BG₂. However, this is forillustrative purposes only, and is not meant to be a limitation of thepresent invention. In an alternative design, the mapper 114 maycategorize more significant bits B₆-B₁₁ as one bit group BG₁, andcategorize less significant bits B₀-B₅ as another bit group BG₂. Inshort, any bit interleaving manner capable of splitting bits of pixeldata of each pixel 201 of the picture 200 into multiple bit groups maybe employed by the mapper 114.

As mentioned above, the pixel data groups DG₁ and DG₂ are transmittedfrom the application processor 102 to the driver IC 104 after undergoingdata compression. Hence, the driver IC 104 obtains one de-compressedpixel data group DG₃ corresponding to the pixel data group DG₁ andanother de-compressed pixel data group DG₄ corresponding to the pixeldata group DG₂ after data de-compression is performed. FIG. 3 is adiagram illustrating a pixel data merging operation performed by thede-mapper 124 based on the first pixel data grouping design. Theoperation of the de-mapper 124 may be regarded as an inverse of theoperation of the mapper 114. Hence, based on the pixel data groupingsetting DG_(SET) employed by the mapper 114, the de-mapper 124 obtains aplurality of bit groups (e.g., two bit groups BG₁ and BG₂ in thisembodiment) from the de-compressed pixel data groups (e.g., twode-compressed pixel data groups DG₃ and DG₄ in this embodiment),respectively, and merge the bit groups to obtain bits of pixel data ofeach pixel 201′ of a reconstructed picture 200′. The resolution of thereconstructed picture 200′ generated at the driver IC 104 is identicalto the resolution of the picture 200 processed in the applicationcircuit 102. Hence, the width of the reconstructed picture 200′ is W,and the height of the reconstructed picture 200′ is H. The pixel data ofeach pixel 201′ of the reconstructed picture 200′ includes a pluralityof bits B₀-B₁₁ corresponding to different bit planes Bit-plane [0]-Bit-plane [11]. For example, each color channel R/G/B of one pixel 201′in the reconstructed 200′ includes 12 bits B₀-B₁₁. The de-mapper 124 mayobtain the bit group BG₁ composed of even bits B₀, B₂, B₄, B₆, B₈, B₁₀of color channels R, G, B of a pixel 201′, obtain another bit group BG₂composed of odd bits B₁, B₃, B₅, B₇, B₉, B₁₁ of color channels R, G, Bof the pixel 201′, and merge the bit groups BG₁ and BG₂ to recover allbits B₀-B₁₁ of the pixel data of the pixel 201′. However, this is forillustrative purposes only, and is not meant to be a limitation of thepresent invention. In another case where the mapper 114 categorizes moresignificant bits B₆-B₁₁ as one bit group BG₁ and categorizes lesssignificant bits B₀-B₅ as another bit group BG₂, the de-mapper 124 mayobtain the bit group BG₁ composed of more significant bits B₆-B₁₁ ofcolor channels R, G, B of a pixel 201′, obtain another bit group BG₂composed of less significant bits B₀-B₅ of color channels R, G, B of thepixel 201′, and merge the bit groups BG₁ and BG₂ to recover all bitsB₀-B₁₁ of the pixel data of the pixel 201′. To put it simply, the bitde-interleaving manner employed by the de-mapper 124 depends on the bitinterleaving manner employed by the mapper 114.

In a second pixel data grouping design, the mapper 114 splits the pixeldata DI of pixels of one picture by dividing complete pixels intodifferent groups. FIG. 4 is a diagram illustrating a pixel datasplitting operation performed by the mapper 114 based on the secondpixel data grouping design. As shown in FIG. 4, the width of a picture400 is W, and the height of the picture 400 is H. Thus, the picture 400has W×H pixels. As shown in FIG. 4, pixels located at the same pixelline (e.g., the same pixel row in this embodiment) include a pluralityof pixels P₀, P₁, P₂, P₃ . . . P_(W−2), P_(W−1). When the second pixeldata grouping design is employed, the display controller 111 controlsthe pixel data grouping setting DG_(SET) to instruct the mapper 114 tosplit pixels of the picture 400 into a plurality of pixel groups (e.g.,two pixel groups PG₁ and PG₂ in this embodiment), and distribute pixeldata of the pixel groups to the pixel data groups (e.g., two pixel datagroups DG₁ and DG₂ in this embodiment), respectively. For example,adjacent pixels located at the same pixel line (e.g., the same pixelrow) are distributed to different groups, respectively. Hence, the pixelgroup PG₁ includes all pixels of even pixel columns C₀, C₂ . . . C_(W−2)of the picture 400, and the pixel group PG₁ includes all pixels of theodd pixel columns C₁, C₃ . . . C_(W−1) of the picture 400. As shown inFIG. 4, the pixel data group DG₁ includes pixel data of H×(W/2) pixels,and the pixel data group DG₂ includes pixel data of H×(W/2) pixels.However, this is for illustrative purposes only, and is not meant to bea limitation of the present invention. In an alternative design, theaforementioned pixel line may be a pixel column. Hence, adjacent pixelslocated at the same pixel column are distributed to different groups,respectively. Hence, the pixel group PG₁ may include all pixels of evenpixel rows of the picture 400, and the pixel group PG₂ may include allpixels of the odd pixel rows of the picture 400. In other words, thepixel data group DG₁ may be formed by gathering pixel data of (H/2)×Wpixels, and the pixel data group DG₂ may be formed by gathering pixeldata of (H/2)×W pixels. To put it simply, any pixel interleaving mannercapable of splitting adjacent pixels of the picture 400 into differentpixel groups may be employed by the mapper 114.

As mentioned above, the pixel data groups DG₁ and DG₂ are transmittedfrom the application processor 102 to the driver IC 104 after undergoingdata compression. Hence, the driver IC 104 obtains one de-compressedpixel data group DG₃ corresponding to the pixel data group DG₁ andanother de-compressed pixel data group DG₄ corresponding to the pixeldata group DG₂ after data de-compression is performed. FIG. 5 is adiagram illustrating a pixel data merging operation performed by thede-mapper 124 based on the second pixel data grouping design. Theoperation of the de-mapper 124 may be regarded as an inverse of theoperation of the mapper 114. Hence, based on the pixel data groupingsetting DG_(SET) employed by the mapper 114, the de-mapper 124 obtainspixel data of a plurality of pixel groups (e.g., two pixel groups PG₁and PG₂ in this embodiment) from the de-compressed pixel data groups(e.g., two pixel data groups DG₃ and DG₄ in this embodiment),respectively, and merge the pixel data of the pixel groups to obtainpixel data of pixels of a reconstructed picture 400′, where adjacentpixels located at the same pixel line (e.g., the same pixel row) of thereconstructed picture 400′ are obtained from different pixel groups,respectively. However, this is for illustrative purposes only, and isnot meant to be a limitation of the present invention. In another casewhere the mapper 114 distributes adjacent pixels located at the samepixel column to different groups, respectively, the de-mapper 124 mayobtain pixel data of a plurality of pixel groups from the de-compressedpixel data groups, respectively, and merge the pixel data of the pixelgroups obtain pixel data of pixels of the reconstructed picture 400′,where adjacent pixels located at the same pixel column of thereconstructed picture 400′ are obtained from different pixel groups,respectively. To put it simply, the pixel de-interleaving manneremployed by the de-mapper 124 depends on the pixel interleaving manneremployed by the mapper 114.

Regarding the second pixel data grouping design mentioned above, thepixels are categorized into different pixel groups in a single-pixelbased manner. In one alternative design, the pixels may be categorizedinto different pixel groups in a pixel section based manner, where eachpixel section includes a plurality of successive pixels located at thesame pixel line (e.g., the same pixel row or the same pixel column).FIG. 6 is a diagram illustrating a first pixel section based pixel datagrouping design according to an embodiment of the present invention.Each of the pixel lines (e.g., pixel rows R₀-R_(H−1) in this embodiment)is divided into a plurality of pixel segments (e.g., two pixel sectionsS₁ and S₂ in this embodiment), and the number of the pixel segmentslocated at the same pixel line is equal to the number of pixel datagroups (e.g., two pixel data groups DG₁ and DG₂ in this embodiment).Concerning the pixel data splitting operation, adjacent pixel segmentslocated at the same pixel line (e.g., the same pixel row in thisembodiment) are distributed to different pixel groups (e.g., two pixelgroups PG₁ and PG₂ in this embodiment), respectively. Hence, as shown inFIG. 6, the pixel group PG₁ is composed of pixel sections S1 eachextracted from one of the pixel rows R₀-R_(H−1) of the picture 400, andthe pixel group PG₂ is composed of pixel sections S2 each extracted fromone of the pixel rows R₀-R_(H−1) of the picture 400.

Concerning the pixel data merging operation, adjacent pixel segmentslocated at the same pixel line (e.g., the same pixel row in thisembodiment) are obtained from different pixel groups (e.g., two pixelgroups PG₁ and PG₂ in this embodiment), respectively. Hence, as shown inFIG. 6, the reconstructed picture 400′ has pixel rows R₀-R_(H−1) eachreconstructed by merging one pixel section S₁ obtained from the pixelgroup PG₁ and another pixel section S₂ obtained from the pixel groupPG₂.

It should be noted that the aforementioned pixel line may be a pixelcolumn in another exemplary implementation. Therefore, each of the pixelcolumns is divided into a plurality of pixel segments, and the number ofthe pixel segments located at the same pixel column is equal to thenumber of pixel data groups. Concerning the pixel data splittingoperation, adjacent pixel segments located at the same pixel column aredistributed to different pixel groups, respectively. Concerning thepixel data merging operation, adjacent pixel segments located at thesame pixel column are obtained from different pixel groups,respectively.

FIG. 7 is a diagram illustrating a second pixel section based pixel datagrouping design according to an embodiment of the present invention.Each of the pixel lines (e.g. , pixel rows R₀-R_(H−1) in thisembodiment) is divided into a plurality of pixel segments (e.g. , fourpixel sections S₁, S₂, S₃ and S₄ in this embodiment), and the number ofthe pixel segments located at the same pixel line is larger than thenumber of pixel data groups (e.g. , two pixel data groups DG₁ and DG₂ inthis embodiment). Concerning the pixel data splitting operation,adjacent pixel segments located at the same pixel line (e.g., the samepixel row in this embodiment) are distributed to different pixel groups(e.g., two pixel groups PG₁ and PG₂ in this embodiment), respectively.Hence, as shown in FIG. 7, the pixel group PG₁ is composed of pixelsections S₁, each extracted from one of the pixel rows R₀-R_(H−1) of thepicture 400, and pixel sections S₃, each extracted from one of the pixelrows R₀-R_(H−1) of the picture 400; and the pixel group PG₂ is composedof pixel sections S₂, each extracted from one of the pixel rowsR₀-R_(H−1) of the picture 400, and pixel sections S₄, each extractedfrom one of the pixel rows R₀-R_(H−1) of the picture 400. Concerning thepixel data merging operation, adjacent pixel segments located at thesame pixel line (e.g., the same pixel row in this embodiment) areobtained from different pixel groups (e.g., two pixel groups PG₁ and PG₂in this embodiment), respectively. Hence, as shown in FIG. 7, thereconstructed picture 400′ has pixel rows R₀-R_(H−1) each reconstructedby merging pixel sections S₁ and S₃ both obtained from the pixel groupPG₁ and pixel sections S₂ and S₄ both obtained from the pixel group PG₂.

It should be noted that the aforementioned pixel line may be a pixelcolumn in another exemplary implementation. Therefore, each of the pixelcolumns is divided into a plurality of pixel segments, and the number ofthe pixel segments located at the same pixel column is larger than thenumber of pixel data groups. Concerning the pixel data splittingoperation, adjacent pixel segments located at the same pixel column aredistributed to different pixel groups, respectively. Concerning thepixel data merging operation, adjacent pixel segments located at thesame pixel column are obtained from different pixel groups,respectively.

FIG. 8 is a flowchart illustrating a control and data flow of the dataprocessing system shown in FIG. 1 according to an embodiment of thepresent invention. Provided that the result is substantially the same,the steps are not required to be executed in the exact order shown inFIG. 8. The exemplary control and data flow may be briefly summarized byfollowing steps.

Step 802: Check a de-compression capability and requirement of a driverIC.

Step 803: Inform an application processor of the de-compressioncapability and requirement.

Step 804: Determine a pixel data grouping setting according to achecking result.

Step 806: Apply rate control to a plurality of compressors,independently.

Step 808: Generate a plurality of compressed pixel data groups by usingthe compressors to compress a plurality of pixel data groups obtainedfrom pixel data of a plurality of pixels of a picture based on the pixeldata grouping setting. For example, the pixel data groups may begenerated based on any of the proposed pixel data grouping designs shownin FIG. 2, FIG. 4, FIG. 6 and FIG. 7.

Step 810: Pack/packetize the compressed pixel data groups into an outputbitstream.

Step 812: Transmit the output bitstream via a display interface.

Step 814: Transmit the pixel data grouping setting via an in-bandchannel (i.e., display interface) or an out-of-band channel (e.g., I²Cbus).

Step 816: Receive the pixel data grouping setting from the in-bandchannel (i.e., display interface) or the out-of-band channel (e.g., I²Cbus).

Step 818: Receive an input bitstream from the display interface.

Step 820: Un-pack/un-packetize the input bitstream into a plurality ofcompressed data groups.

Step 822: Generate pixel data of a plurality of pixels of areconstructed picture by using a plurality of de-compressors tode-compress the compressed pixel data groups, independently, and thenmerging a plurality of de-compressed pixel data groups based on thepixel data grouping setting.

It should be noted that steps 802 and 804-814 are performed by theapplication processor (AP) 102, and steps 803 and 816-822 are performedby the driver IC 104. As a person skilled in the art can readilyunderstand details of each step shown in FIG. 8 after reading aboveparagraphs, further description is omitted here for brevity.

Moreover, the proposed data parallelism scheme may be inactivated whenusing a single compressor at the AP side and a single de-compressor atthe driver IC side is capable of meeting the throughput requirement. Forexample, the application processor may refer to information of thede-compression capability and requirement informed by the driver IC todecide the throughput M (pixels per clock cycle) of one de-compressor inthe driver IC and the target throughput requirement N (pixels per clockcycle) of the display panel driven by the driver IC. Assume that thethroughput of one compressor in the application processor is also M(pixels per clock cycle). When N/M is not greater than one, this meansthat using a single compressor at the AP side and a single de-compressorat the driver IC side is capable of meeting the throughput requirement.Hence, the proposed data parallelism scheme is inactivated, and theconventional rate-controlled compression and de-compression isperformed. When N/M is greater than one, this means that using a singlecompressor at the AP side and a single de-compressor at the driver ICside is unable to meet the throughput requirement. Hence, the proposeddata parallelism scheme is activated. In addition, the number ofcompressors enabled in the application processor and the number ofde-compressors enabled in the driver IC may be determined based on thevalue of N/M.

The pixel data splitting operation performed by the mapper 114 is togenerate multiple pixel data groups that will undergo rate-controlledcompression independently. However, it is possible that pixel data ofadjacent pixel lines (e.g., pixel rows or pixel columns) in the originalpicture are categorized into different pixel data groups. The ratecontrol generally optimizes the bit rate in terms of pixel contextrather than pixel positions. The pixel boundary may introduce artifactssince the rate control is not aware of the boundary position. Taking thepixel data grouping design shown in FIG. 6 for example, the rate controlapplied to the pixel section S₁ of the pixel row R₀ is independent ofthe rate control applied to the pixel section S₂ of the same pixel rowR₀. Specifically, the pixel section S₁ is compressed in an order from P₀to P_(M), and the pixel section S₂ is compressed in an order fromP_(M+1) to P_(W−1). Concerning the pixels P_(M) and P_(M+1) on oppositesides of the pixel boundary between pixel sections S₁ and S₂, the pixelP_(M) may be part of a compression unit with a first bit budgetallocation, and the pixel P_(M+1) may be part of another compressionunit with a second bit budget allocation different from the first bitbudget allocation. The difference between the first bit budgetallocation and the second bit budget allocation may be large. As aresult, the rate controller 116 may allocate bit rates un-evenly on thepixel boundary, thus resulting in degraded image quality on the pixelboundary in a reconstructed picture. To avoid or mitigate the imagequality degradation caused by artifacts on the pixel boundary, thepresent invention further proposes a position-aware rate controlmechanism which optimizes the bit budget allocation in terms of pixelpositions.

FIG. 9 is a diagram illustrating a position-aware rate control mechanismaccording to an embodiment of the present invention. As shown in FIG. 9,there are compression units CU₁ and CU₂ on one side of a pixel boundaryand compression units CU₃ and CU₄ on the other side of the pixelboundary. The compression units CU₁ and CU₂ belong to one pixel groupPG₁, and the compression unit CU₁ is nearer to the pixel boundary thanthe compression unit CU₂. The compression units CU₃ and CU₄ belong toanother pixel group PG₂, and the compression unit CU₃ is nearer to thepixel boundary than the compression unit CU₄. In one exemplaryembodiment, each of the compression units CU₁-CU₄ may include 4×2pixels, and the compression units CU₁-CU₄ may be horizontally orvertically adjacent in a picture. When the position-aware rate controlmechanism is activated, the rate controller 116 may be configured toadjust the bit rate control according to a position of each pixelboundary between different pixel groups. For example, the ratecontroller 116 increases an original bit budget BBori_CU₁ assigned tothe compression unit CU₁ by an adjustment value Δ1 (Δ1>0) to therebydetermine a final bit budget BBtar_CU₁, and decreases an original bitbudget BBori_CU₂ assigned to the compression unit CU₂ by the adjustmentvalue Δ1 to thereby determine a final bit budget BBtar_CU₂. In addition,the rate controller 116 increases an original bit budget BBori_CU₃assigned to the compression unit CU₃ by an adjustment value Δ2 (Δ2>0) tothereby determine a final bit budget BBtar_CU₃, and decreases anoriginal bit budget BBori_CU₄ assigned to the compression unit CU₄ bythe adjustment value Δ2 to thereby determine a final bit budgetBBtar_CU₄. The adjustment value Δ2 maybe equal to or different from theadjustment value Δ1, depending upon actual design consideration. Sincethe proposed position-aware rate control tends to set a larger bitbudget near the pixel boundary, the artifacts on the pixel boundary canbe reduced. In this way, the image quality around the pixel boundary ina reconstructed picture can be improved.

In a case where the position-aware rate control is employed, the flowshown in FIG. 8 may be modified to have step 806 replaced with thefollowing step shown in FIG. 10.

Step 1002: Apply rate control to a plurality of compressors according topixel boundary positions, independently.

As a person skilled in the art can readily understand details of step1002 after reading above paragraphs, further description is omitted herefor brevity.

Taking the pixel data grouping design shown in FIG. 6 for example, therate control applied to the pixel section S₁ of the pixel row R₀ isindependent of the rate control applied to the pixel section S₂ of thesame pixel row R₀. The pixel section S₁ is compressed in an order fromP₀ to P_(M), and the pixel section S₂ is compressed in an order fromP_(M+1) to P_(W−1). As a result, the bit budget allocation condition forthe pixel P_(M) (which is the last compressed pixel in the pixel sectionS₁) may be different from the bit budget allocation condition for thepixel P_(M+1) (which is the first compressed pixel in the pixel sectionS₂). To avoid or reduce artifacts on the pixel boundary, the presentinvention further proposes a modified compression mechanism withcompression orders set based on pixel boundary positions. FIG. 11 is adiagram illustrating a modified compression mechanism according to anembodiment of the present invention. As shown in FIG. 11, there arecompression units CU₁ and CU₂ on one side of a pixel boundary andcompression units CU₃ and CU₄ on the other side of the pixel boundary.The compression units CUand CU₂ belong to one pixel group PG₁, and thecompression unit CU₁ is nearer to the pixel boundary than thecompression unit CU₂. The compression units CU₃ and CU₄ belong toanother pixel group PG₂, and the compression unit CU₃ is nearer to thepixel boundary than the compression unit CU₄. In one exemplaryembodiment, each of the compression units CU₁-CU₄ may include 4×2pixels, and the compression units CU₁-CU₄ may be horizontally orvertically adjacent in a picture. When the modified compressionmechanism is activated, each of the compressors 115_1 and 115_2 may beconfigured to set a compression order according to a position of eachpixel boundary between different pixel groups. For example, thecompressor 115_1 compresses the compression unit CU₁ prior tocompressing the compression unit CU₂, and the compressor 115_2compresses the compression unit CU₃ prior to compressing the compressionunit CU₄. In other words, two adjacent pixel sections located at thesame pixel line are compressed in opposite compression orders. Since themodified compression scheme starts the compression from compressionunits near the pixel boundary between adjacent pixel groups, the bitbudget allocation conditions near the pixel boundary may be moresimilar. In this way, the image quality around the pixel boundary in areconstructed picture can be improved. When the modified compressionmechanism is activated at the AP side, the de-mapper 124 at the driverIC side may be configured to further consider the compression orderswhen merging the de-compressed pixel data groups DG₃ and DG₄.

In a case where the modified compression mechanism is employed, the flowshown in FIG. 8 may be modified to have step 808 replaced with thefollowing step shown in FIG. 12.

Step 1202: Generate a plurality of compressed pixel data groups bysplitting pixel data of a plurality of pixels of a picture into aplurality of pixel data groups based on the pixel data grouping settingand using the compressors to compress the pixel data groups according tocompression orders set based on pixel boundary positions.

As a person skilled in the art can readily understand details of step1202 after reading above paragraphs, further description is omitted herefor brevity.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A data processing apparatus, comprising: amapper, configured to receive pixel data of a plurality of pixels of apicture, and split the pixel data of the pixels of the picture into aplurality of pixel data groups; a plurality of compressors, configuredto compress the pixel data groups and generate a plurality of compressedpixel data groups, respectively; and an output interface, configured topack the compressed pixel data groups into at least one outputbitstream, and output the at least one output bitstream via a displayinterface.
 2. The data processing apparatus of claim 1, whereincompression operations performed by the compressors are independent ofeach other.
 3. The data processing apparatus of claim 2, furthercomprising: a rate controller, configured to apply bit rate control tothe compressors, respectively.
 4. The data processing apparatus of claim1, wherein the display interface is a display serial interface (DSI)standardized by a Mobile Industry Processor Interface (MIPI) or anembedded display port (eDP) standardized by a Video ElectronicsStandards Association (VESA).
 5. The data processing apparatus of claim1, wherein pixel data of each pixel of the picture includes a pluralityof bits corresponding to different bit planes, and the mapper isconfigured to split the bits of the pixel data of each pixel of thepicture into a plurality of bit groups, and distribute the bit groups tothe pixel data groups, respectively.
 6. The data processing apparatus ofclaim 1, wherein the mapper is configured to split the pixels of thepicture into a plurality of pixel groups, and distribute pixel data ofthe pixel groups to the pixel data groups, respectively.
 7. The dataprocessing apparatus of claim 6, wherein adjacent pixels located at asame pixel line of the picture are distributed to different pixelgroups, respectively.
 8. The data processing apparatus of claim 6,wherein adjacent pixel segments located at a same pixel line of thepicture are distributed to different pixel groups, respectively, andeach of the adjacent pixel segments includes a plurality of successivepixels.
 9. The data processing apparatus of claim 8, wherein at leastone pixel line of the picture is divided into a plurality of pixelsegments, and a number of the pixel segments is equal to a number of thepixel data groups.
 10. The data processing apparatus of claim 8, whereinat least one pixel line of the picture is divided into a plurality ofpixel segments, and a number of the pixel segments is larger than anumber of the pixel data groups.
 11. The data processing apparatus ofclaim 6, further comprising: a rate controller, configured to apply bitrate control to the compressors, respectively; wherein the ratecontroller adjusts the bit rate control according to a position of eachpixel boundary between different pixel groups.
 12. The data processingapparatus of claim 11, wherein concerning a specific pixel boundarybetween a first pixel group and a second pixel group, the ratecontroller is configured to increase an original bit budget assigned toa first compression unit by an adjustment value and decrease an originalbit budget assigned to a second compression unit by the adjustmentvalue; the first compression unit and the second compression unit areadjacent compression units in any of the first pixel group and thesecond pixel group; and the first compression unit is nearer to thespecific pixel boundary than the second compression unit.
 13. The dataprocessing apparatus of claim 6, wherein each of the compressors isfurther configured to set a compression order according to a position ofeach pixel boundary between different pixel groups.
 14. The dataprocessing apparatus of claim 13, wherein concerning a specific pixelboundary between a first pixel group and a second pixel group, a firstcompressor is configured to compress a first compression unit prior tocompressing a second compression unit, and a second compressor isconfigured to compress a third compression unit prior to compressing afourth compression unit; the first compression unit and the secondcompression unit are adjacent compression units in the first pixelgroup, and the first compression unit is nearer to the specific pixelboundary than the second compression unit; and the third compressionunit and the fourth second compression unit are adjacent compressionunits in the second pixel group, and the third compression unit isnearer to the specific pixel boundary than the fourth compression unit.15. The data processing apparatus of claim 1, wherein the dataprocessing apparatus is coupled to another data processing apparatus viathe display interface; and the data processing apparatus informs theanother data processing apparatus of a pixel data grouping settingemployed to split the pixel data of the pixels of the picture.
 16. Thedata processing apparatus of claim 1, wherein the data processingapparatus is coupled to another data processing apparatus via thedisplay interface, and the data processing apparatus further comprises:a controller, configured to check a de-compression capability andrequirement of the another data processing apparatus, and determines anumber of the pixel data groups in response to a checking result.
 17. Adata processing apparatus, comprising: an input interface, configured toreceive at least one input bitstream from a display interface, andun-pack the at least one input bitstream into a plurality of compressedpixel data groups of a picture; a plurality of de-compressors,configured to de-compress the compressed pixel data groups and generatea plurality of de-compressed pixel data groups, respectively; and ade-mapper, configured to merge the de-compressed pixel data groups intopixel data of a plurality of pixels of the picture.
 18. The dataprocessing apparatus of claim 17, wherein de-compression operationsperformed by the de-compressors are independent of each other.
 19. Thedata processing apparatus of claim 17, wherein the display interface isa display serial interface (DSI) standardized by a Mobile IndustryProcessor Interface (MIPI) or an embedded display port (eDP)standardized by a Video Electronics Standards Association (VESA). 20.The data processing apparatus of claim 17, wherein pixel data of eachpixel of the picture includes a plurality of bits corresponding todifferent bit planes, and the de-mapper is configured to obtain aplurality of bit groups from the de-compressed pixel data groups,respectively, and merge the bit groups to obtain the bits of the pixeldata of each pixel of the picture.
 21. The data processing apparatus ofclaim 17, wherein the de-mapper is configured to obtain pixel data of aplurality of pixel groups from the de-compressed pixel data groups,respectively, and merge the pixel data of the pixel groups to obtain thepixel data of the pixels of the picture.
 22. The data processingapparatus of claim 21, wherein adjacent pixels located at a same pixelline of the picture are obtained from different pixel groups,respectively.
 23. The data processing apparatus of claim 21, whereinadjacent pixel segments located at a same pixel line of the picture areobtained from different pixel groups, respectively, and each of theadjacent pixel segments includes a plurality of successive pixels. 24.The data processing apparatus of claim 23, wherein at least one pixelline of the picture is obtained by merging a plurality of pixelsegments, and a number of the pixel segments is equal to a number of thede-compressed pixel data groups.
 25. The data processing apparatus ofclaim 23, wherein at least one pixel line of the picture is obtained bymerging a plurality of pixel segments, and a number of the pixelsegments is larger than a number of the de-compressed pixel data groups.26. The data processing apparatus of claim 17, wherein the dataprocessing apparatus is coupled to another data processing apparatus viathe display interface; and the data processing apparatus receives apixel data grouping setting of splitting the pixel data of the pixels ofthe picture from the another data processing apparatus.
 27. The dataprocessing apparatus of claim 17, wherein the data processing apparatusis coupled to another data processing apparatus via the displayinterface, and the data processing apparatus further comprises: acontroller, configured to inform the another data processing apparatusof a de-compression capability and requirement of the data processingapparatus.
 28. A data processing method, comprising: receiving pixeldata of a plurality of pixels of a picture, and splitting the pixel dataof the pixels of the picture into a plurality of pixel data groups;compressing the pixel data groups to generate a plurality of compressedpixel data groups, respectively; and packing the compressed pixel datagroups into at least one output bitstream, and outputting the at leastone output bitstream via a display interface.
 29. A data processingmethod, comprising: receiving at least one input bitstream from adisplay interface, and un-packing the at least one input bitstream intoa plurality of compressed pixel data groups of a picture; de-compressingthe compressed pixel data groups to generate a plurality ofde-compressed pixel data groups, respectively; and merging thede-compressed pixel data groups into pixel data of a plurality of pixelsof the picture.